This invention relates to a fault-diagnosing method for an electronic computer, and more particularly to an improved fault-diagnosing method provided with a bus for an exclusive diagnosis of a fault.
The conventional fault-diagnosing apparatus for an electronic computer has generally been designed to inform a fault-diagnosing unit of the state of the respective sections of the electronic computer through data paths provided for the execution of the normal function of the electronic computer.
FIG. 1 schematically illustrates a prior art electronic computer provided with a fault-diagnosing apparatus operated by utilizing the above-mentioned data path. There will now be described the concrete arrangement of the known electronic computer shown in FIG. 1. A scratch pad memory 1 is connected directly to a main data path 6. Groups 2, 3 of registers are connected to the main data path 6 indirectly through a shifter 4 and an arithmetic logic operation unit (ALU) 5. To the main data path 6 is connected a main memory 7 through a write data register 8. A fault-diagnosing unit 9 is connected to the data path 6.
The prior art fault-diagnosing apparatus based on the utilization of the main data path 6 of FIG. 1 can indeed effectively diagnose faults occurring in the respective data-processing sections of an electronic computer. Where, however, only a very little output signal is produced by a section, for example, a sequential circuit formed of a complicated combination of memory elements and logic elements collectively to perform a large function or a section carrying out a particular definite function, then considerable difficulties arise in efficiently diagnosing faults simply by utilizing the data bus provided for the execution of the normal function of an electronic computer.
To date, various improved fault-diagnosing apparatuses have been proposed. One of these apparatuses is the type in which an exclusive signal line for diagnosis of a fault is provided between a fault-diagnosing unit and the main flip-flop circuits of the electronic computer control circuits which are to be diagnosed for efficient diagnosis of a fault if occurring in any of said control circuits. Another proposed fault-diagnosing apparatus is the type in which a plurality of memory elements are connected in the form of a loop at the time of diagnosing a fault to facilitate said diagnosis.
FIG. 2 schematically shows the arrangement of the proposed electronic computer in which signal lines are set between a fault-diagnosing unit and the main flip-flop circuit of control circuits being diagnosed. With the fault-diagnosing unit of FIG. 2, control circuit 20 is formed of a plurality of packages 21-1 through 21-n. The circuit in the package 21-1 may be assumed to consist of a plurality of flip-flop circuits 23 combined with combinational circuits 22 for supplying input signals to said flip-flop circuits 23. The other packages 21-2 through 21-n are each likewise formed of a plurality of flip-flop circuits combined with combinational circuits for supplying input signals to said flip-flop circuits (not shown). Selectors 24-1 through 24-n are provided for the respective packages 21-1 through 21-n to send status signals of flip-flops 23 to the fault-diagnosing unit 25. The input terminals of the fault-diagnosing selectors 24-1 through 24-n are connected to the flip-flop circuits 23. The faul-diagnosing selectors 24-1 through 24-n pick up one of the flip-flop circuits 23 according to the control signals supplied from the fault-diagnosing unit 25 through a selection control line 26. In the case of a plurality of output lines 27-1, . . . 27-n, a group of flip-flops 23 are selected. A signal indicating the state of the selected flip-flop circuit 23 is transferred to the fault-diagnosing unit 25 through one of output signal lines 27-1 through 27-n.
FIG. 3 schematically indicates the concrete system arrangement of another proposed electronic computer in which the memory elements of the control circuit being diagnosed are connected in the form of a loop at the time of fault diagnosis. The arrangement of FIG. 3 differs from that of FIG. 2 only in that the output terminals of all the flip-flop circuits 23 of the packages 21-1 through 21-n are connected together in the form of a loop and that the loop has its contents shifted by one bit, each time a clock pulse is received from the fault-diagnosing unit 25, thereby causing the state of the respective flip-flop circuits to be read out to the fault-diagnosing unit 25. For convenience of description, the flip-flop circuits 23 and combinational circuits 22 included in the packages 21-1 through 21-n were arranged as illustrated in FIGS. 2, 3 and 5. Actually, however, the flip-flop circuits 23 are included in registers provided in the control circuits of an electronic computer, and the combinational circuits 22 represent those which supply an input signal to said registers. The registers and the combinational circuits 22 are constituents of a sequential circuit. The sequential circuit is generally formed of the type shown in FIG. 4. The sequential circuit of FIG. 4 comprises a register 100 and a combinational circuit 200. This sequential circuit is so arranged that an output signal from the register 100 is fed back to the combinational circuit 200. The flip-flop circuits of FIGS. 2, 3 and 5 represent the respective one-bit sections (R.sub.1 to R.sub.n) of the register 100. Generally, each of the control circuits of an electonic computer contains a plurality of sequential circuits. At least one sequential circuit is provided in each package. FIGS. 2, 3 and 5 show a sequential circuit typified by flip-flop circuits. The reason is that this invention primarily relates to means for indicating the interior condition of a sequential circuit in order to diagnose a fault occurring therein.
FIGS. 2 and 3 show only four of the flip-flop circuits 23 included in the respective packages 21-1 through 21-n. Generally, a single package contains ten and odd flip-flop circuits. Further, the respective packages 21-1 through 21-n often issue several to about ten bits for fault diagnosis.
However, the proposed fault-diagnosing apparatuses shown in FIGS. 2 and 3 have the following drawbacks. Referring to the fault-diagnosing apparatus of FIG. 2, a large number of input signal lines 27-1 through 27-n are connected to the fault-diagnosing unit 25. Though a logic circuit tends to be integrated with higher density due to the recent development of semiconductor techniques, yet it is impossible easily to increase the number of the input-output terminal pins of the packages. Therefore, the actual design of an electronic computer is often subject to limitations due to the impossibility of readily increasing said input and output terminal pins. Where an electronic computer is designed to render the whole of it compact and efficient, reduction in the number of input and output terminal pins becomes a very important problem. Further, the fault-diagnosing unit has to be provided with some means by which said unit can selectively send forth an output signal.
The control circuit shown in FIG. 3 provided with a fault-diagnosing unit 25 has the drawbacks that through a fewer number of input signals are supplied to said fault-diagnosing unit 25, yet it is necessary to provide special flip-flop circuits which can be operated not only at the ordinary mode, but also can act as shift registers at the time of diagnosis of faults; and that since the states of the respective flip-flop circuits 23 are read out in the specified order only by one bit each time, diagnosis of faults has to be effected by a complicated procedure.
Some commercially available IC part of an electronic computer is the type which has a selector function and can have a wired OR or bus arrangement, with the output terminal provided with an open collector circuit or try-state circuit. However, where, with either of the above-mentioned bus arrangements, the output terminal of any one of the constituent elements is short-circuited, then it is said that no effective method is now available to detect a constituent element which has become faulty.
The wired OR arrangement or bus arrangement has the drawback that where constituent elements increase in number, then the stray capacity of, for example, wiring also becomes large, causing the transmission of a signal to be much delayed. Namely, with the ordinary circuit, the waveform of a signal sharply rises or falls as indicated in broken line in FIG. 6. But the wired OR arrangement or bus arrangement in which a large number of packages are connected together has the drawback that the waveform of a signal rises or falls very gently as shown in solid line in said FIG. 6.